This invention relates generally to system area networks (SAN), and more particularly the invention relates to a peripheral controller in a SAN which supports multiple concurrent data channels with reduced read latency over the SAN.
System Area Networks using data packet switching are well known and in use today. The ServerNet of the Tandem Computer Group of Compaq Computer Corporation is a System Area Network which can employ two switch interconnect fabrics (X, Y) in a packet switch, point to point network with an address space supporting over a million end nodes where each end node can communicate directly with any other end node. FIG. 1 is a functional block diagram of the ServerNet with the two X, Y fabrics (router nodes) 10, 12, interconnecting the end nodes 14 which typically include CPUs, I/O controllers and PC work stations. While two fabrics can provide highly reliable, clustered configurations, only one fiber is architecturally required.
A plurality of peripheral components can be connected to one end node of the ServerNet through a peripheral component interface or PCI. Heretofore, a plurality of peripherals have been connected through a common bus to a PCI unit through which system Read requests from the peripherals are channeled. Typically, a peripheral given access to the bus will tie up the bus until a data request is completed. Moreover, the peripheral will remain in an idle state until the data is retrieved. Additionally, because of data limits in packet switching, a peripheral can be required to make a plurality of data requests in completing a data exchange transaction.
The present invention is directed to a PCI which supports multiple, simultaneous data channels with reduced Read latency in transactions initiated by an end node.
In accordance with the invention, a PCI connects a plurality of peripheral devices to end nodes on the system fabric through a plurality of internal independent channels. A peripheral requesting a data transaction in the network is assigned one of a plurality of PCI data channels for use in the transaction. The channel remains assigned to the peripheral until the transaction is completed. Thus, by using the plurality of channels, a plurality of data transactions can be supported simultaneously for one or more peripherals coupled to the PCI.
In accordance with the invention, latency in effecting data transactions is reduced by several features of the invention. When a Read request is received from a peripheral by the PCI, local PCI memory is first accessed for the data, and if the data is not present a channel is assigned to the peripheral for the transaction. The peripheral is then instructed to relinquish the bus and retry the request at a later time. Other peripherals can then have access to the PCI through the bus for requesting data transactions. Meanwhile, the data is requested from the network through the assigned channel, and once the data becomes available it is transferred through the assigned channel for storage in the local PCI memory.
To further reduce latency, Read transactions are scheduled ahead of time for the most recently active requestor so that Read data is already present in the local end node memory when it is being requested. Thus, Read latency over the SAN can be eliminated entirely for subsequent Read transactions thereby greatly improving overall system performance.
The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawings.